Using FSMC (Flexible Static Memory Controller) is straight forward as you set up the FSMC I/O and just access the memory directly. What happens is that FSMC Address and Data pins suddenly start clocking on the pins. But, how do I sample ?
I was first looking for some kind of “magical” burst technique in FSMC before it hit me that the one I am looking for is memory to memory DMA. I should be able to use the DMA directly from the I/O pins on the FSMC Data to SPI. The datasheet actually confirms this. This will allow me to sample at the speed of the SPI which in the case of a M4 is 42Mbit/s. The actual sample time will be lower since we need to adapt to an available Raspberry PI speed.
It is a huge difference between sample frequency and the frequency you can monitor. The reason is because you need an absolute minimum of two samples per Hz. The reality is that the more samples you get the more accurate your Logic Analyzer will be. This is why I actually am interested in 100Mhz because it would give me a fairly accurate monitoring capability at 10Mhz and a very high accuracy at 1Mhz. But, it is no way we can transfer 100Msps so we need to do smart filtering and trigger mechanism’s on the MCU.
I can use an external SRAM to sample with larger depth than the internal SRAM will allow me, but as this also uses FSCM we will be down at 50Mhz since the DMA need to do two operations. A second issue is that as we write we will be sending logic on the same pins we use for reading, so we need additional electronics to avoid that.
I was planning to use STM32F405Rx for this because it is a neat 64 pin MCU, but I notice that FSCM is only available on 100 pin and larger. In which case I can as well use the faster STM32F427.
I am however not sure if I want to go forward with this at all. It is doable, but the cost of using these large and expensive MCU’s makes me wonder if it would be better and cheaper to pick up a FPGA. I will however do the testing since I have the chips and the concept interest me.