CPU load in out case is a definition – if I say that a cycle time of 100yS (0,00001 Sec) is 100% CPU Load then the data above indicate we have 10% CPU Load – if we say 1ms is 100% we are at 1% CPU load. We use in average 10 yS to execute a cycle where we check all tasks and max is 25-27 yS. This is with my own barebone linear RTOS.
I currently use Putty as terminal on the PC to communicate with CLI on the board. It also allows me to Print tekst directly from the embedded application. As USB is 12Mbps it is pretty fast – I can print sufficiently fast to basically get my PC stressed out printing. I will create a specialized terminal i BSA later so I can log printing as well and have several channels.
CLI is in this case connected through USB, but I will add TCP a bit later. The command set is rather simple, but I can read and write single variables as well as tables. A bit later I will add FW download this way as well.
The reason I do these stats is because I need to see how reliable I can expect to execute tasks, and the numbers above indicate 10yS with some cycles up in 30yS, meaning 30yS or lets say 100yS is a very reliable call frequency. I will double check my math a bit because I would like to understand why some cycles take 27yS. It is two reasons possible – (1) the tasks uses a bit of extra time on one cycle, or (2) I have interrupts influencing the cycle. In this case I have an USB interrupt that I suspect, but I will prove that. I don’t really need this level of timing schemes on this CAN Hub, but I like to understand the numbers I get. To verify this I will snapshot the cycle data then I detect I 27yS cycle and analyze that cycle. I have start/stop times in cycle and every single task so it’s not that difficult.
Understanding the performance I have is also key to design and understanding how design will affect the total performance because I still have a lot of software to add/activate.
Just a footnote that the extra long cycle is interrupts feeding USB. Also as I switched to Release the average cycle dropped to 4yS.